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   &#160;<span id="projectnumber">1.2.2-120323</span>
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<div class="title">GPIO_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div>  </div>
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<p>General Purpose I/O.  
</p>

<p><code>#include &lt;<a class="el" href="stm32f4xx_8h_source.html">stm32f4xx.h</a>&gt;</code></p>
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<tr><td colspan="2"><h2><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_g_p_i_o___type_def.html#a2b671a94c63a612f81e0e9de8152d01c">MODER</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_g_p_i_o___type_def.html#a9543592bda60cb5261075594bdeedac9">OTYPER</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_g_p_i_o___type_def.html#a328d16cc6213783ede54e4059ffd50a3">OSPEEDR</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_g_p_i_o___type_def.html#abeed38529bd7b8de082e490e5d4f1727">PUPDR</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_g_p_i_o___type_def.html#a328d2fe9ef1d513c3a97d30f98f0047c">IDR</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_g_p_i_o___type_def.html#abff7fffd2b5a718715a130006590c75c">ODR</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_g_p_i_o___type_def.html#aa79204c9bcc8c481da0a5ffe7c74d8b0">BSRRL</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_g_p_i_o___type_def.html#a35f89f65edca7ed58738166424aeef48">BSRRH</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_g_p_i_o___type_def.html#a2612a0f4b3fbdbb6293f6dc70105e190">LCKR</a></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_g_p_i_o___type_def.html#ab67c1158c04450d19ad483dcd2192e43">AFR</a> [2]</td></tr>
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<hr/><h2>Field Documentation</h2>
<a class="anchor" id="ab67c1158c04450d19ad483dcd2192e43"></a><!-- doxytag: member="GPIO_TypeDef::AFR" ref="ab67c1158c04450d19ad483dcd2192e43" args="[2]" -->
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          <td class="memname">__IO uint32_t <a class="el" href="struct_g_p_i_o___type_def.html#ab67c1158c04450d19ad483dcd2192e43">AFR</a>[2]</td>
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<p>GPIO alternate function registers, Address offset: 0x20-0x24 </p>

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<a class="anchor" id="a35f89f65edca7ed58738166424aeef48"></a><!-- doxytag: member="GPIO_TypeDef::BSRRH" ref="a35f89f65edca7ed58738166424aeef48" args="" -->
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<p>GPIO port bit set/reset high register, Address offset: 0x1A </p>

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<a class="anchor" id="aa79204c9bcc8c481da0a5ffe7c74d8b0"></a><!-- doxytag: member="GPIO_TypeDef::BSRRL" ref="aa79204c9bcc8c481da0a5ffe7c74d8b0" args="" -->
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<p>GPIO port bit set/reset low register, Address offset: 0x18 </p>

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<a class="anchor" id="a328d2fe9ef1d513c3a97d30f98f0047c"></a><!-- doxytag: member="GPIO_TypeDef::IDR" ref="a328d2fe9ef1d513c3a97d30f98f0047c" args="" -->
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          <td class="memname">__IO uint32_t <a class="el" href="struct_g_p_i_o___type_def.html#a328d2fe9ef1d513c3a97d30f98f0047c">IDR</a></td>
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<p>GPIO port input data register, Address offset: 0x10 </p>

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<a class="anchor" id="a2612a0f4b3fbdbb6293f6dc70105e190"></a><!-- doxytag: member="GPIO_TypeDef::LCKR" ref="a2612a0f4b3fbdbb6293f6dc70105e190" args="" -->
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<p>GPIO port configuration lock register, Address offset: 0x1C </p>

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<a class="anchor" id="a2b671a94c63a612f81e0e9de8152d01c"></a><!-- doxytag: member="GPIO_TypeDef::MODER" ref="a2b671a94c63a612f81e0e9de8152d01c" args="" -->
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<p>GPIO port mode register, Address offset: 0x00 </p>

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<a class="anchor" id="abff7fffd2b5a718715a130006590c75c"></a><!-- doxytag: member="GPIO_TypeDef::ODR" ref="abff7fffd2b5a718715a130006590c75c" args="" -->
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          <td class="memname">__IO uint32_t <a class="el" href="struct_g_p_i_o___type_def.html#abff7fffd2b5a718715a130006590c75c">ODR</a></td>
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<p>GPIO port output data register, Address offset: 0x14 </p>

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<a class="anchor" id="a328d16cc6213783ede54e4059ffd50a3"></a><!-- doxytag: member="GPIO_TypeDef::OSPEEDR" ref="a328d16cc6213783ede54e4059ffd50a3" args="" -->
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<p>GPIO port output speed register, Address offset: 0x08 </p>

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<a class="anchor" id="a9543592bda60cb5261075594bdeedac9"></a><!-- doxytag: member="GPIO_TypeDef::OTYPER" ref="a9543592bda60cb5261075594bdeedac9" args="" -->
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<div class="memdoc">
<p>GPIO port output type register, Address offset: 0x04 </p>

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<a class="anchor" id="abeed38529bd7b8de082e490e5d4f1727"></a><!-- doxytag: member="GPIO_TypeDef::PUPDR" ref="abeed38529bd7b8de082e490e5d4f1727" args="" -->
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<p>GPIO port pull-up/pull-down register, Address offset: 0x0C </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>D:/123/stm32f4_blink_led-1.2.2-120323/inc/<a class="el" href="stm32f4xx_8h_source.html">stm32f4xx.h</a></li>
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